Superposition feedback decoding algorithm for parallel concatenated block code based on correlation operation 并行级联分组码基于相关运算的叠加反馈译码
To avoid excessive error feedback that may cause decoding failure, both outer and inner iterations are used. 为防止过多错误反馈造成译码失效,提出采用内、外双重迭代方式来提高系统的鲁棒性。
4D 8-state trellis encoding of 1000 Base-T provides 6 dB coding gain in an inter-symbol interfere ( ISI) and noise free channel. Decision feedback sequence estimator ( DFSE) is used for post-cursor ISI compensation, noise erasion and decoding. 千兆以太网的四维8状态网格编码提供了无干扰无噪声情况下的6dB信噪比增益,判决反馈时序估计电路被用于消除后馈干扰、抑制噪声及译码。
Next, according to the characteristics of quasi-cyclic matrix, a new encoding circuit using feedback shift registers is proposed and implemented by FPGA. Thirdly, the decoding algorithm and decoder implementation are studied. 接着,针对生成矩阵的准循环特性,提出了一种新的基于反馈移位寄存器的编码电路,并用FPGA进行了实现。再次,论文对译码算法和译码器实现进行了研究。